1. Field of the Invention
The present invention relates to a delay circuit applied to, for example, a gate-array large-scale integrated circuit (LSI).
2. Description of the Related Art
In a gate-array LSI, a delay circuit is used for delaying the propagation of a signal for a definite time period. Such a delay circuit must offer an optimum delay time period, a small mounting area, and minimum fluctuation of the delay time period.
In general, a delay time period t.sub.pd of one gate of a metal-insulator-semiconductor (MIS) transistor can be represented by EQU t.sub.pd .alpha.C/g.sub.m
where C is a load, capacitance, and g.sub.m is the conductance of the transistor. Further, if the load capacitance is definite, EQU g.sub.m .alpha.W/L
where W and L are the width and length, respectively, of a gate of the transistor. Therefore, it is possible to increase the delay time period by using an inverter of MIS transistors having a small gate width W and a large gate length L. However, in a gate-array LSI, since only transistors having a definite size are used, it is impossible to arbitrarily change the size of the transistors. In other words, in a gate-array LSI, it is impossible to decrease the gate width W and increase the gate length L only for special transistors.
There is a prior art delay circuit of a gate-array LSI comprised of a series of inverters of MIS transistors having a definite size. However, when a series of such inverters are simply connected to obtain a delay time period, the larger the delay time period, the greater the number of transistors, and thus the larger the area occupied.
Note that it is also possible to construct a delay circuit by using a resistance-capacitance (RC) circuit. In this case, the delay time period must be adjusted by the resistance of polycrystalline silicon or the resistance of a diffusion region. However, such an adjustment is also impossible in a gate-array LSI. Accordingly, it is impossible to use an RC circuit as a delay circuit for a gate-array LSI.